In recent years, fine structure and integration have progressed rapidly particularly in the field of semiconductor memory. As the degree of integration is increased, however, it becomes increasingly difficult to maintain manufacture yield. Redundancy techniques have been used as a means for maintaining the manufacture yield of semiconductor devices. In a redundancy technique, a fuse is formed as a portion of the semiconductor device. This fuse may include, for example, a plurality of memory elements. When a defective portion of a memory cell is discovered, the fuse is cut according to the size of the defective portion of the memory cell. For instance, based on the number of defective memory elements, the fuse may be partitioned by the cut such that the defective memory elements may be replaced by an appropriate number of memory elements in the fuse. Using this technique, the defective memory cells are effectively replaced with spare memory cells and the defective memory cells are remedied.
FIG. 1 is a block diagram showing, schematically, the construction of a semiconductor device. As shown in FIG. 1, the semiconductor device 100 has a plurality of memory macros MM10 to MM50 formed on the same semiconductor substrate as a large scale integration (LSI). The term “macro” means a functional block comprising an aggregate of elements that together perform a particular function. These macros are connected to each other by a chip interior wiring and comprise a system LSI.
In addition to a memory block 110, each of the memory macros MM10 to MM50 includes a fuse block 120 having a plurality of fuse elements used in redundancy. Each of the memory macros MM10 to MM50 also includes a control circuit 130. The fuse element and the control circuit, included within each of the memory macros MM10 to MM50, are used to remedy a memory cell included within a respective memory macro MM10 to MM50.
This system of including individual fuse elements and control circuits in every memory macro is inefficient. Particularly, it is impossible to commonly use any of the fuse elements between different macros. This type of device also lacks area efficiency because a control circuit must be arranged every macro. Further, because a writing operation of the fuse element is performed by a laser blow, and because the laser cannot penetrate areas including bumps, no bumps may be placed in an area of the fuse block corresponding to each of the memory macros MM10 to MM50. This requirement greatly impacts the design of the semiconductor device and makes bump layout difficult. For instance, in the device shown in FIG. 1, formation inhibiting areas A10 to A50, which correspond to the fuse blocks of each of the memory macros, designate areas where bumps cannot be formed. These formation inhibiting areas A10 to A50 are scattered at random on the semiconductor substrate face, and as a result, bump arrangement is greatly restricted.
A structure, as shown in FIG. 2, has been proposed to solve the above problems. FIG. 2 is a block diagram showing the schematic construction of a semiconductor device having plural memory macros. In this construction, a fuse element and a control circuit are separated from each of memory macros MM60 to MM80. Both the fuse element and the control circuit are commonly used in each of the memory macros MM60 to MM80. For example, as shown in FIG. 2, fuse block 140 and control circuit 150 are serially wired to a shift register 160 arranged in each of the memory macros MM60 to MM80.
This construction, however, is also problematic. With respect to the arrangement of bumps, because the fuse block 140 is included in a corner portion of the semiconductor substrate, this corner portion must be absent of bumps. Like the above-described device, bump arrangement is greatly restricted. Further, stresses are particularly concentrated at the corner portion of the semiconductor substrate. These stresses can significantly degrade the reliability of the fuse element. Further, Because the wiring distance between the fuse and each memory macro is different, delay times and resistance values in the wiring between the fuse and each memory macro are different. These differences negatively impact the electric characteristics of the semiconductor device.